Predictable composition of memory accesses on many-core processors

Quentin Perret (1, 2) , Pascal Maurère (2) , Éric Noulard (1) , Claire Pagetti (1) , Pascal Sainrat (3) , Benoît Triquet (2)

1 ONERA - The French Aerospace Lab [Toulouse]
2 Airbus [France]
3 IRIT-TRACES - Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués

The use of many-core COTS processors in safety critical embedded systems is a challenging research topic. The predictable execution of several applications on those processors is not possible without a precise analysis and mitigation of the possible sources of interference. In this paper, we identify the external DDR-SDRAM and the Network on Chip to be the main bottlenecks for both average performance and predictability in such platforms. As DDR-SDRAM memories are intrinsically stateful, the naive calculation of the Worst-Case Execution Times (WCETs) of tasks involves a significantly pessimistic upper-bounding of the memory access latencies. Moreover, the worst-case end-to-end delays of wormhole switched networks cannot be bounded without strong assumptions on the system model because of the possibility of deadlock. We provide an analysis of each potential source of interference and we give recommendations in order to build viable execution models enabling efficient composable computation of worst-case end-to-end memory access latencies compared to the naive worst-case-everywhere approach.

Keywords: many-core processor; real-time; composition rules; execution model; DDR-SDRAM; Network on Chip

Domains: Embedded Systems

Quentin Perret, Pascal Maurère, Éric Noulard, Claire Pagetti, Pascal Sainrat, et al.. Predictable composition of memory accesses on many-core processors. 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan 2016, TOULOUSE, France. ⟨hal-01256000⟩